Memory systems typically employ large amounts of DRAM memory as main memory. At the transistor level, a DRAM cell is a capacitor structure, with the capability of maintaining a charge representing a “bit” on the order of approximately 64 ms. To maintain the charge, the cell needs to be periodically refreshed—generally involving a read and write operation every 64 ms. Conventionally, the entire DRAM array is blindly refreshed even though much of the memory may not be active. Conventional refresh operations can consume as much as a third of the power consumption associated with the memory.
While DRAMs traditionally employ hardware-based refresh operations at very high rates, a variety of other memory technologies provide fast access times similar to DRAM, but with much slower refresh rate requirements. For example, some forms of RRAM can operate with refresh rates on the order of seconds. Slower refresh rates can also be beneficial for memory technologies that are susceptible to repetitive write operations that can degrade cell retention.
Thus, the need exists for an improved refresh scheme for memory systems that can minimize power dissipation and take advantage of reduced-rate refresh requirements.
Like reference numerals refer to corresponding parts throughout the drawing figures.